Technical Field
The invention relates to a video processing apparatus, and particularly relates to a video processing apparatus capable of effectively distribute a plurality of memory bandwidths and a video processing circuit thereof.
Related Art
Along with quick development of technology, since a current video processing system is required to process and decode high-definition video data, for example, a transmission bandwidth of 5 Gbytes/s is required to decode a video stream with high-definition image quality (for example, HD, UHD, 4K2K, etc.), the video processing system having a video decoder (or an encoder, a decoder) and/or a video processor generally requires a higher memory bandwidth to load the high-definition video data.
Generally, when the video processor writes a reconstructed video frame into a memory, and reads other video frames from the memory to conduct some modifications (for example, edge enhancement, noise reduction, image scaling, etc.), a problem of memory bandwidth congestion is probably encountered due to frequent accessing of the same memory, which may influence a performance of the video decoder.